The present invention relates to a method of generating a test pattern for a semiconductor integrated circuit with which the semiconductor integrated circuit is tested by using a scanning method for a delay anomaly occurring during the manufacturing thereof and to a method of testing the semiconductor integrated circuit by using the generated test pattern.
With the rapid advancement of a miniaturizing technique used in a semiconductor process in recent years, semiconductor integrated circuits have been increased sharply in scale and function, which makes it more difficult to test the semiconductor integrated circuits. As a solution to the problem, a scanning method and the like have been used widely as techniques for facilitating the testing of the semiconductor integrated circuits so that a fault represented by a stuck fault model is tested efficiently. In the case of detecting a fault assumed to be the stuck fault model, a fault detecting ability is not dependent on the frequency of a clock signal for synchronization so that a scan test is normally conducted by using a clock frequency lower than the actual operating speed.
However, process variations have become more distinct as smaller geometries have been defined in the semiconductor process, so that sufficient testing quality is not guaranteed by merely conducting a test in accordance with a conventional scanning method using a low clock frequency. As a replacement, a test considering a signal delay on a signal path, such as a path delay test using the same clock frequency as used during actual operation has been in greater demand. For example, Japanese Unexamined Patent Publication No. HEI 9-269959 discloses a technique used in a conventional path delay test.
The conventional path delay test has been performed by assuming a fault model in which a delay value on a signal path is increased by a defect produced in the manufacturing process, i.e., a fault model in which a signal which should normally reach a terminal point of the signal path in one clock period is prevented by the defect from reaching the terminal point in one clock period.
However, the conventional path delay test has not been performed by assuming a fault model in which the delay value is reduced excessively against expectations by the defect produced in the manufacturing process (hereinafter referred to as an excessively reduced delay).
In a synchronous semiconductor integrated circuit, the following two phenomena can be listed as factors which distinguish the defect produced in the manufacturing process as the excessively reduced delay.
(1) Propagation of a signal along a signal path between flip-flops which is faster than a design value.
(2) Variations in the skew value of a clock supplied to each of the flip-flops via different clock lines.
If such phenomena occur, the signal path between the flip-flops undergoes a mis-operation termed a hold error (data retention error).
The two factors will be described herein below with reference to the drawings.
FIG. 7 partially shows a semiconductor integrated circuit to be tested. As shown in FIG. 7, a combinational circuit 103 containing at least one combinational logic element is disposed between first and second flip-flops 101 and 102 each having a data input terminal D, a data output terminal Q, and a clock input terminal CK. One of a plurality of signal paths connecting the first and second-flip-flops 101 and 102 is designated at 104. The clock input terminal CK of the first flip-flop 101 is connected to a first clock line 106 via a first clock tree buffer 105. The clock input terminal CK of the second flip-flop 102 is connected to a second clock line 108 via a second clock tree buffer 107.
FIGS. 8A to 8C show signal waveforms illustrating the operation of the semiconductor integrated circuit of FIG. 7, of which FIG. 8A shows the case where the degree of delay on a signal path 104 is in a normal range, FIG. 8B shows the case where a fault is caused by an excessively reduced delay with which a signal propagates along the signal path 104 faster than a design value, and FIG. 8C shows the case where a skew resulting from variations in delay value occurs between the first and second clock lines 106 and 108.
As shown in FIG. 8A, a delay value on the signal path 104 is determined at the design stage to allow a hold margin A for the second flip-flip 102 even when the signal propagates at a highest expected speed. At this stage, the sizes, locations, and the like of the first and second clock tree buffers 106 and 107 are adjusted such that the amount of skew of a clock signal on each of the first and second clock lines 106 and 108 becomes zero or nearly zero.
However, if the signal on the signal path 104 propagates at a speed not higher than the delay value determined at the design stage due to the factor (1) resulting from variations or a defect in the process of manufacturing a semiconductor integrated circuit as shown in FIG. 8B, the second flip-flop 102 undergoes a hold error, which may cause the mis-operation of the second flip-flop 102.
Even when the delay value on the signal path 104 is normal, if the first clock tree buffer 105, the second clock tree buffer 107, the first clock line 106, or the second clock line 108 suffers a defect or variations during the manufacturing thereof and the clock signal on the clock line 106 or 108 develops a skew due to the factor (2) as shown in FIG. 8C, the second flip-flop 102 latches by mistake the signal after the transition from the first flip-flop 101 so that a mis-operation occurs.
If any of the signal paths undergoes a mis-operation due to a defect produced in the manufacturing process, it is necessary to conduct a test for detecting a fault on the signal path and generate a test pattern to be used in the test.
It is therefore an object of the present invention to allow the generation of a test pattern necessary for the testing of a scan-designed semiconductor integrated circuit for an excessively reduced delay and allow a test for the excessively reduced delay.
To attain the foregoing object, a first method of generating a test pattern for a semiconductor integrated circuit according to the present invention assumes a method of generating a test pattern for a semiconductor integrated circuit comprising a logic circuit containing a combinational logic element, a first sequential circuit having an output side connected to an input side of the logic circuit, and a second sequential circuit having an input side connected to an output side of the logic circuit, whereby a test pattern for testing a signal path between the first and second sequential circuits for a data retention error associated with data held by the second sequential circuit based on output data of the second sequential circuit is generated, the method comprising the steps of: generating a first test pattern by setting, at the first sequential circuit, a first set value for the signal path such that the signal path is activated immediately before and after one pulse of a clock signal for synchronization is inputted; and generating a second test pattern by setting, at the first sequential circuit, a second set value obtained by inverting the first set value.
In accordance with the first method of generating a test pattern for a semiconductor integrated circuit, the first test pattern is generated by setting, at the first sequential circuit, the first set value for the signal path such that the signal path is activated immediately before and after one pulse of the clock signal for synchronization is inputted and the second test pattern is generated by setting, at the first sequential circuit, the second set value obtained by inverting the first set value. This allows testing when a mis-operation results from a data retention error due to an excessively reduced delay on the signal path to be tested.
A second method of generating a test pattern for a semiconductor integrated circuit according to the present invention assumes a method of generating a test pattern for a semiconductor integrated circuit comprising first and second logic circuits each containing a combinational logic element, a first scan register having an input side connected to an output side of the first logic circuit and an output side connected to an input side of the first logic circuit, and a second scan register having an input side connected to an out put side of the second logic circuit, whereby a test pattern for testing a signal path between the first and second scan registers for a data retention error associated with data held by the second scan register based on output data of the second scan register is generated, the method comprising the steps of: setting, at the first scan register, a first set value as an output value thereof; generating a first test pattern by performing an implication operation with respect to the first or second logic circuit based on the first set value; setting, at the first scan register, a second set value obtained by inverting the first set value as an input value thereof; generating a second test pattern by performing an implication operation with respect to the first or second logic circuit based on the second set value; and generating a scan test pattern by combining the first and second test patterns such that the signal path is activated immediately before and after one pulse of a clock signal for synchronization is inputted.
In accordance with the second method of generating a test pattern for a semiconductor integrated circuit, the first test pattern is generated by performing the implication operation with respect to the first or second logic circuit connected to the first scan register based on the first set value set as the output value of the first scan register. Subsequently, the second test pattern is generated by performing the implication operation with respect to the first or second logic circuit based on the second set value set as the input value of the first scan register and obtained by inverting the first set value. Subsequently, one scan test. pattern is generated by combining the first and second test patterns, such that the signal path to be tested is activated immediately before and after one pulse of the clock signal for synchronization is inputted. If one pulse of the clock signal for synchronization is given not for a scan operation but for a normal operation, therefore, the logic of the signal suffers no contradiction before and after the one pulse. This allows testing when a mis-operation results from a data retention error due to an excessively reduced delay on the signal path to be tested.
A method of testing a semiconductor integrated circuit according to the present invention assumes a method of testing a semiconductor integrated circuit comprising a logic circuit containing a combinational logic element, a first scan register having an output side connected to an input side of the logic circuit, and a second scan register having an input side connected to an out put side of the first logic circuit, whereby a signal path between the first and second scan registers is tested for a mis-operation resulting from a data retention error associated with data held by the second scan register, the method comprising the steps of: preparing a test pattern to be inputted to the signal path; selecting a scan path containing the first and second scan registers; performing a scan-in operation with respect to the selected scan path to input the test pattern to the scan path; performing a capture operation with respect to the scan path by using one pulse of a clock signal for synchronization to input, to the scan path, a propagation signal propagating along the signal path and activated immediately before and after the one pulse; and performing a scan-out operation with respect to the scan path to output, from the second scan register, the propagation signal as a result of the testing.
In accordance with the method of testing the semiconductor integrated circuit of the present invention, the scan-in operation is performed with respect to the scan path to input, to the scan path, the test pattern according to the present invention that has been prepared in advance. Subsequently, the scan path is caused to perform not a scan operation but the capture operation, which is an actual operation, by using one pulse of the clock signal for synchronization so that the propagation signal propagating along the signal path activated immediately before and after the one pulse is inputted directly to the second scan register from the first scan register with no intervention of another scan register. This allows a test for the delay of the propagation signal actually propagating along the signal path to be tested and thereby allows testing when a mis-operation results from a data retention error due to an excessively reduced delay on the signal path to be tested. This is because an output signal of the first scan register is not necessarily inputted directly to the second scan register and may be outputted to another scan register since the scan path test is conducted by using a shift register composed only of a plurality of scan registers. Even when a frequency lower than the clock frequency for an actual operation is used, the real-time property of the testing method according to the present invention is not impaired.